Common building blocks called Symmetrix VMAX™ engines. Each engine has dual integrated Virtual Matrix Directors providing its own CPU, Memory, and Cache resources, along with front end (to host) and back end (to physical storage) ports. The EMC® Virtual Matrix Architecture™ is a new way to build storage systems that Each Symmetrix VMAX director consolidates front-end, global memory, and. The Symmetrix V-Max family includes 2 options for scalability and growth. The V-Max series scales from 48 to 2, disks and provides 2 Peta.


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Vmax Engine Rear View: Vmax architecture example displays the rear view of the V-Max Engine. Using these ports all directors communicate through the Virtual Matrix via redundant connections.

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One Vmax engine with storage bay: In this example,Engine vmax architecture has two half populated Storage Bays. This allows for a total of drives.

EMC VMAX Architecture

In this example, the system has been expanded to include Engine 5. Back end module provide access to the disk drives. Each Vmax engine has two SIBs and vmax architecture has two vmax architecture.

Director port connection to MIBE.

Storage World: VMAX architecture

System bay contains all Vmaxengines. The example I am using is the EMC Symmetrix line, but the concepts here could be applied vmax architecture other systems if details were available. The basic information here is from the EMC documents. vmax architecture

Because the details on the internal architecture of the VMAX is not found in a single authoritative source, much of it has to be pieced together. Some of the assessments here are speculation, so anyone with hard knowledge is invited to provide corrections. Each engine is comprised of a pair of directors.

The vmax architecture with 2 directors has vmax architecture back-end FC ports 2 ports making 1 loop and can have 16 ports on the front-end in the FC configuration. Then in theory, the combined front-end and back-end bandwidth vmax architecture the full system is 16 x 3.


Of vmax architecture, there is no documentation on the actual sequential or large block IO capability of the V-Max system. To support the above director, I would guess that the system architecture should have 6 vmax architecture PCI-E slots.

Based on a quad-port FC HBA, the 8 back-end ports requires 2 x8 slots, and there are also 2 x8 slots for the front-end for any supported interface.

Without discussing the nature of the interconnect between directors in an engine, and the Virtual Matrix Interface, I am supposing that each requires one x8 slot. The above vmax architecture does show a connection between the two directors in one engine.

It could also be presumed that the slots are not connected through an expander, as this would result in an vmax architecture with unbalanced bandwidth. At this point I would like to digress to review the Intel Core2 system architecture.

The original memory controller hub MCH or chipset for vmax architecture 2-socket Core2 system was the P inpins.


So this is clearly inadequate to support the VMAX director. This MCH chipset was not used by any server system vendor, so why did Intel make it if there were no vmax architecture customers?


It is possible the MCH was built vmax architecture to the requirements of the high-end storage system vendors. I mentioned this briefly in System Vmax architecture Q3. I think this is done by using the ESI plus 1 x4 on the upstream side of the Enterprise South Bridge to support x8 on the downstream side.